A Guiding Compass for Memory Designers Navigating the Uncharted Territory of DDR5
As high-speed digital standards evolve to keep up with the latest technologies, from 5G and Internet of Things (IoT) to artificial intelligence and autonomous vehicles, hardware engineers working in memory design are encountering many new challenges. Specifically, the need for faster double data rate (DDR) memory architectures has created a demand for more bandwidth and lower latencies in data centers. As the industry transitions from DDR4 memory to DDR5, a practical, simulation-based design and analysis workflow will be critical for memory designers.
DDR4, first released in 2014, is the most common memory device type. It provides higher bandwidth, increased speed and increased power efficiency, compared to its predecessors. Yet with these advantages comes new obstacles, including extra complexity, longer simulation time and shrinking design margins. In turn, it’s more difficult to correlate simulation and test data, which decreases design confidence and results in longer troubleshooting cycles. Now, with DDR5 emerging on the horizon, transfer speeds and memory are expected to double. All of the challenges that DDR4 invited will become even more pronounced with DDR5.
Fortunately, a practical, simulation-based design and analysis workflow solution now offers a compass for memory designers navigating the uncharted territory of DDR5. For the first time, DDR5 will have equalization on the DRAM receiver. This leaves engineers with the challenge of finding out how they will simulate this and how they will find the optimal equalization tabs in a reasonable amount of time. Troubleshooting questions are also bound to follow: Can the simulation provide an accurate model? Can engineers avoid potential roadblocks ahead of manufacturing? The list goes on, adding to why a simulation tool is crucial.
To achieve optimal success in DDR memory design, engineers should seek a simulation tool that checks all of the following boxes:
- Captures critical effects such as crosstalk and accurately predicts eye closure caused by jitter
- Supports input/output buffer information specification (IBIS) models and allows all measurements to be applied to a group of signals that can be viewed at one time
- Provides an integrated simulation and test workflow
- Allows for quick and actionable insight into simulated waveforms, well before a prototype is built
- Provides one schematic to be used for both DDR bus simulation and transient simulation to significantly decrease setup time
- Enables the use of simple wiring to automatically match and connect components, using information from the layout to help connect an IBIS file
- Allows for the same test bench for pre-layout and post-layout flow and easy electromagnetic (EM) simulation of many nets at once
- Supports use of a universal probe for measurements at any node
For more detail on what memory designers should look for in a simulation-based design and workflow analysis solution, read this white paper, “Designing for DDR4 and Beyond.” For more technical depth, watch the accompanying on-demand webinar.