PathWave Celebrates 25th DesignCon with New Offerings for High-Speed Digital Designers
2020-01-15 | 6 min read
This year marks the 25th anniversary of DesignCon. It seems like only yesterday that I attended the first edition, but I admit that my memory of the proceedings and exhibits has faded. What I do recall is that back in the mid-nineties, chip and system designers were making the transition to language-based methods and the issue of the day was design verification. Design complexity was increasing dramatically with the new abstraction level and the amount of time engineers had to spend in functional verification was skyrocketing. There wasn’t enough time in the design cycle or verification resources to finish all the tests needed to ensure success.
Fast-forward to 2020, and high-speed digital designs are much more complex. Today’s design and test issues revolve around validating signal integrity, power integrity, and sharing huge amounts of data between teams. When you visit Keysight’s DesignCon booth and attend our show activities later this month, what you’ll see and hear from the PathWave software team is laser-focused on the challenges that engineers face in creating and validating high-speed digital designs.
For example, Heidi Barnes, our industry-recognized expert on the subject of signal and power integrity, will host a boot camp on Tuesday, January 28th where you can engage in a hands-on experience tackling these issues. Visit “Relating SI and PI for High-Speed Digital Boards: FPGA DDR4 Case Study” for more details.
In our booth #725, the PathWave team will conduct several software demonstrations including signal integrity analysis, power integrity analysis, simulation of DDR5 with IBIS-AMI modeling, and design and test workflow. Look for a major product announcement about our new DDR5 simulation and modeling capabilities before checking out the demonstration. We’ll also have an exciting giveaway specially created to commemorate the DDR5 announcement available to booth visitors during our happy hour event at 3:00 pm Wednesday, January 29th. Stop by and celebrate with us.
Don’t miss the design and test workflow demonstration which leverages the recently introduced PathWave Desktop Edition, Keysight’s platform that addresses data sharing through connected, agile workflows. Here’s a more detailed description to pique your interest.
Challenge: Layout engineers produce printed circuit board (PCB) artwork for thousands of signal nets, and tens of power/ground nets. At this pre-production validation stage, it is a daunting task for any signal integrity engineer to review and verify that each signal trace performs as desired. Simple mistakes can easily creep into the artwork, such as moving a group of signal traces from one layer to another, while forgetting to adjust trace width.
The impact of the mistake is that the impedance changes, degrading the performance of the signal. This simple mistake has a tangible cost to the development cycle. Typically, signal integrity engineers avoid this predicament by analyzing several traces at once with an electromagnetic (EM) simulator, but the sheer scale of modern-day designs means that many more signal traces are left unverified, which can increase production risks and possibly product slippage.
Solution: However, what if a designer had access to a quick scan of all of the nets to check for gross routing errors? For example, what if the designer could analyze all the traces in an automated way, then compare the results to target specs such as insertion loss, electrical length, and characteristic (Z0) impedance of the traces? Then if any particular traces were identified as being close to the limit (or failing), they could easily be reviewed with high-accuracy EM solutions.
As later iterations of the same design become available, the same test suite could be automated to re-run, ensuring that no failures creep into the design; in other words, regression testing for electrical performance on the PCB design. Finally, what if this automated system could equally compare simulated data to measured data, to improve confidence in the design sign-off process?
The Demo: a new Z0 scanner for the PathWave design and test workflow. The scanner uses fast EM extraction techniques to automatically extract key electrical performance parameters for very large numbers of signal nets at once. The automated process requires very minimal input from the user and the results can be visually compared to spec limits previously entered. After reviewing the validation dashboard, the user can choose to use SIPro EM, a feature of PathWave ADS – to further examine critical nets. With both EM technologies at work, the user has much greater confidence in not having missed performance issues in the design, while maximizing the workflow efficiency.