5 Ways to Overcome Signal and Power Integrity Challenges with Simulation
2018-08-28 | 10 min read
Engineers continue to face major challenges when it comes to signal and power integrity in modern day high-speed systems. These often include higher device integration, lower IC supply voltages, smaller real estate on the PCB, and more. Advanced software can help power integrity engineers overcome these issues through simulation. These simulation solutions can provide a variety of services that can help in ways such as improving high-speed link performance in PCB designs. Below are five possible software solutions to some of the most common Signal Intensity/Power Intensity (SI/PI) problems that designers face.
1. Simplify the use of S-parameter files for parts
There are several things to consider after downloading an S-parameter file for a part. With a high-speed connector for a backplane for example, it has many ports. The first step is often inspecting the quality of the data and then using it in a simulation. This brings up questions about how to wire it up and which ports are paired.
Traditionally, the answer might be to open the data in a text editor. Programs such as ADS’s S-Parameter Checker simplify the process and allow designers to view the contents of any S-parameter file without having to setup an S-parameter test bench simulation. This allows them to directly plot the individual relations they wish to see, and shows them the port names against each pin. It also tells designers if the file is passive or reciprocal, as well as the number of data points in the file and the frequency range it covers. Designers can even use S-Parameter Checker to rename, re-order and reduce the number of ports, which enables them to save a new, more usable S-parameter file (Figure 1).
2. Stay ahead of technology waves (such as PAM-4)
Market pressures on IP routers set an expectation to do more at a lower cost per bit. However, to go faster and provide a single 100-Gbps electrical lane across the distance of a typical backpane is beyond present day technology.
The solution lies in Pulsed-Amplitude Modulation (PAM) for high speed serial links. PAM increases the bit throughput on serial channels and effectively doubles the data rate for a link bandwidth. It represents a revolutionary step in the industry, but comes with its own unique set of challenges as well. For example, we can transmit a PAM-4 symbol at 28 Gbaud and deliver 56 Gbps at the other end, but the IC's use more power and the signal itself has a reduced Signal-to-Noise ratio (SNR). ADS helps with challenges such as managing complexity while reducing production cost, or researching how to go further and faster on low-loss materials and fabrication processes.
3. Enable flat PDN impedance responses
Once the initial pre-layout design has been created, the first-pass of the PCB layout can be imported into ADS for analysis using PIPro EM technology. The user interface allows designers to select the power and ground nets for the PDN network they want to simulate, choose simulation models for each of the components (e.g., decaps, EMI filters, inductors, and resistors, etc.), and setup the PI-AC simulator to compute the PDN impedance of the distributed layout with components in place.
Since the PI-AC simulator has EM technology designed specifically for this purpose, a very accurate result is returned in minutes. Designers can then use the field visualization, PDN impedance and S-parameter plotting to determine if there are problems with the current PDN design, and to check coupling from one capacitor to the next. A schematic representation is generated to transfer the EM-characterized model, together with circuit models of the components. This back-annotation to an ADS Schematic enables one smooth cohesive workflow. Designers can then apply their behavioral VRM model, and further tune the decaps for final verification/optimization.
4. Enable electro-thermal simulation
As power delivery networks are forced into tighter PCB real-estate, the power plane becomes far from idealized. Usually the once perfect plane is perforated heavily with clearance holes from stitching vias, and it can be a struggle for the layout engineer to get the required current up into the package of the device that requires it, without passing through narrow traces of metal. Calculating an accurate IR-Drop is important for the PI designer, but also knowing the absolute temperature that the PDN traces, vias and chip die will reach, is invaluable information. High temperatures can cause reliability issues; as the temperature cycles from on/off states can cause the via barrels to weaken and crack over time.
It is not intuitive to the designer whether a via is undersized for the current that is passing through it. The temperature rise is very dependent on the width of the traces attached to it. Secondly, resistance of a trace increases with temperature, requiring simulation analyses to determine the final steady state condition. For every 10 degC change in temperature we see a 4% change in resistance of a trace. These observations point to a need to simulate the PDN design with a DC IR Drop electro-thermal solution.
ADS provides a fully-automated integrated Electrical-Thermal-Electrical iterative simulation. Users receive an accurate representation of DC IR Drop results by factoring in local resistivity changes due to heating. The additional Thermal-only simulation, gives the user the ability to perform thermal floor planning.
With ADS you can copy existing DC IR Drop simulation setup to new Electro-Thermal simulation and visualize a list the temperature of planes, pins and vias.
5. Use an interconnect toolbox
The signal integrity design challenge is not just to successfully recover the transmitter signal at the receiver, but to understand what is controlling the performance. It’s important to find the significant margin eaters and the ones that can be optimized.
Typical connections between a transmitter and a receiver include some section of application specific custom PCB routing. ADS has a signal integrity tool box to help explore the design trade-offs and deal with the complex interaction between stack-up, transmission line losses, and via topology.
Designing the PCB interconnect starts with some sort of PCB stack-up definition in order to start evaluating the different types of possible transmission line topologies. Once the transmission lines are optimized for impedance and losses, then one needs to look at via performance to transition between layers. Anyone of these steps has cost and performance trade-offs that can impact the other, resulting in a complex inter-relationship to determine which feature is the real margin eater: Layer Count, Line Z, Via Backdrills, Material, Layout Density, etc.
ADS provides an Interconnect Tool Box that includes Substrate Editor, Controlled Impedance Line Designer, and Via Designer to simplify the pre-layout PCB interconnect investigation.