Industry Insights

Relief From the Worst 400GE Measurement Pains

2019-09-24  |  4 min read 

The move from NRZ-based 100G interfaces to PAM4-based 400GE interfaces is revolutionary, rather than evolutionary: New technologies such as linear broadband amplifiers and drivers as well as adaptive digital equalizers have become a mandatory part of the design but are not sufficient to ensure error-free operation. 400GE links typically operate at rather high intrinsic bit error rates (BER) and forward error correction (FEC) is therefore required.

The combination of adaptive equalization and FEC has drastically increased the level of complexity in the characterization and validation of silicon devices, application-specific integrated circuits (ASICs), fiber and copper interconnects, optical transceivers, and the port electronics of switches and routers. Identifying potential performance and interoperability issues at an early stage is critical as answers are complex and time-consuming to solve.

The main challenge to test 400GAUI-8 interfaces here is until now to generate the prescribed stress on the lane under test, while providing the correct unstressed data patterns on the adjacent seven data lines requires to support the striped FEC required by the host FEC decoder on the host chip. For 400G optical transceiver module designers it has been a pain to verify the frame loss ratio (FLR) within the specified limits.

Keysight is now introducing the N4891A / 400GE-QDD, the industry’s first 400GE FEC aware RX test solution, causing ample relief.

The solution combines the versatile and accurate M8040A 64 Gbaud high-performance BERT to provide the stressed pattern to the lane under test, along with the A400G-QDD 400GE multiport module tester from Ixia to produce the striped pattern on the adjacent aggressor lanes, with the perfect synchronization, and allows bit error ratio (BER) and FLR measurements.

High signal integrity RF components allow to take full advantage of the 400GE multiport module tester four QSFP-DD ports, enabling R&D & validation engineers to support a large variety of test setups: such as electrical or optical receiver tests for components or optical transceiver modules. 

It empowers the industry to accelerate the deployment of next generation 400GE devices in the datacenters. It provides unique insights to understand how component and system design tradeoffs are affected by Forward Error Correction (FEC) requirements and to predict the system margin under real conditions. This solution allows measurement of frame loss ratio in 400G Ethernet links using FEC by supplying one stressed lane, while maintaining the proper FEC striped test pattern data, without stress on the other lanes.

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