The Need for Speed
2019-01-31 | 4 min read
Massive data flow from 5G, artificial intelligence (AI), virtual reality (VR), Internet of Things (IoT), and autonomous vehicles is driving explosive traffic growth, creating unprecedented demand for bandwidth everywhere in the network and data center. Consumers no longer tolerate even the smallest delay to data access. In some applications, such as autonomous driving and medical IoT devices, delayed communication can lead to life and death situations.
100GE is common in data centers today, but it will not be fast enough to support the increased demand for bandwidth and speed. As a result, many data center operators have begun migrating their networks to 400GE. Faster networking speeds require faster memory and faster serial bus communications.
In parallel with transceiver upgrades to 400GE, data center operators need a migration plan that will enable the next generation of high-speed computing interfaces (e.g., PCIe or DDR). PCIe expansion bus speeds will move from PCIe 4.0 to PCIe 5.0 to support 400GE speeds. The same is true for memory as DDR moves from DDR4 to DDR5.
PCI Express evolves to PCIe 5.0
PCIe 4.0, with a data rate of 16 gigatransfers per second (GT/s), is no longer sufficient to support 400GE speeds. As a result, the PCI Special Interest Group (PCISIG), the standard body that defines the PCI Express specifications, has fast-tracked the development of the PCIe 5.0 standard which is due for completion later this year. With a data rate of 32 GT/s, PCIe 5.0 provides twice the throughput of PCIe 4.0.
DDR5 doubles the data rate of DDR4
DDR4 is designed for the computing server industry and supports data transfer speeds up to 3.2 GT/s. The Joint Electronic Devices Engineering Council (JEDEC), the organization that defines the DDR specifications, is currently working on the next generation of DDR memory, DDR5, to fulfill the need for faster data rates. DDR5 will operate at data rates up to 6.0 GT/s or higher and will effectively double the data rate of DDR4.
Emerging new standards offer alternatives
New interconnect standards, such as OpenCAPI, Gen-Z, and CCIX, designed to optimize specific data transfer functions, provide alternatives to PCIe yet introduce another level of complexity for high-speed digital designers. Increasing the speed of serial data communications requires high-speed precision testing at every level.
Each generational change of high-speed computing standards provides new features and faster data transfer rates, creating new test challenges for digital designers. The need to measure complex specifications complicates the design and validation process and requires a long learning curve for test engineers. Since standards evolve quickly from one generation to the next, test engineers can save significant time and get their designs to market faster using test solutions that ensure full compliance with industry standards.
Learn more about the evolution of high-speed computing interfaces and find solutions to address your design and test challenges here.