Author | Keysight Blogs

Stephanie Michel 2019.08.06

DDR5 and the special requirements regarding receiver testing raise a lot of questions. A big field here is the possible test fixtures. What will be an adequate channel to connect the tester to your de

1 min read

#DDR5 #Gen 5 #Data Center Infrastructure

Industry Insights

Stephanie Michel 2019.07.02

With margins getting tighter, DDR5 is the first generation of DDR with a standardized receiver test. This may cause some insecurities not only about the requirements and definitions that your design m

1 min read

#Data Center Infrastructure #Gen 5 #DDR5

Industry Insights

Stephanie Michel 2019.06.21

When you notice the short period of time elapsed between PCI Express Gen4 and Gen5, you may wonder how many changes in specs have actually occurred. A big step lies in doubling signal speeds from 16 G

1 min read

#PCIe #PCIe 5.0 #Gen 5 #Data Center Infrastructure

Industry Insights

Stephanie Michel 2019.06.04

PCI Express 4.0 has been ratified less than 2 years ago, and Gen 5 is already approaching. Why so fast? Rick Eads, member of the PCI-SIG board of directors, explains the motivation behind PCI Express

1 min read

#PCIe 5.0 #Gen 5 #Data Center Infrastructure

Industry Insights

Stephanie Michel 2019.02.15

Forward Error Correction [1] is becoming ubiquitous in the data-center. Not only in 400G links, where SNR requirements to achieve error-free transmission using PAM4 modulation cannot be met anymore,

3 min read

#PAM4 #400GE #Data Center Infrastructure

Industry Insights

Stephanie Michel 2018.11.27

Photonic integrated circuit (PIC) and silicon photonics technologies are being used to manufacture devices for optical communications at higher volumes with lower costs, energy consumption, and size.

7 min read

#Data Center Infrastructure #Lightwave Component Analyzers #Optical + Photonic #Tunable Laser Sources

Stephanie Michel

DDR 5 – Answers to the Test Fixture Questions

DDR5 Receiver Testing And What It Is All About

What Are the Differences Between PCI Express 4.0 and PCI Express 5.0?

Why Does PCI Express 5.0 Come So Shortly After PCI Express 4.0?

PAM4 And How Forward Error Correction (FEC) Produces Relief - And New Problems

Silicon Photonics: Tricks and Tweaks for Wafer and Chip-Level Optical Test